Advances in processing technology and demands for greater complexity at reduced cost and power-consumption points have lead to continual increases in densities. As geometries scale signal paths become closer together, a side effect of this scaling is that coupling capacitance between wires becomes the dominant portion of the total wire capacitance. See, K. L. Shepard, “Design methodologies for noise in digital integrated circuits”, Proceedings of the Design Automation Conference, pages 94-99, June 1998; and F. Dartu, L. Pileggi, “Calculating worst-case gate delays due to dominant capacitance coupling”, Proceedings of the Design Automation Conference, pages 46-51, June 1997. At the same time, the signal transition times have become faster resulting in stronger aggressors on adjacent victim wires. See, F. Dartu et al, supra. Another side effect of process advancement is the faster scaling of cell internal delay than the interconnect delay, making accurate analysis of interconnect delay important.
With the manufacturing processes moving into the nanometer technology domain for very large scale integrated (VLSI) circuits, signal integrity (SI), or the ability for signals transmitted and processed by an electrical system to tolerate a certain level of noise interference, has become extremely important to the success of the manufactured VLSI product. As such, immunity is turning into a metric of the same importance as power, area and timing because it directly influences all of them.
When neighboring nets switch, the coupling capacitors cause a transfer of charge between them. Depending on the relative times and directions of switching, the amount of crosstalk noise varies. The net that is affected by the noise is known as a victim net, while the neighboring nets that affect it are known as aggressor nets. Noise faults may manifest themselves as functional noise faults, or glitches, in which victim nets take incorrect values. They may also manifest themselves as delay noise faults in which correct transitions on victim nets are delayed or sped up. FIG. 1A is a diagram illustrating one example of a circuit where functional noise, or a glitch 4, is induced on the victim net 12 due to a rising transition 6 on the aggressor net 10. The glitch 4 causes a fault 2 at the output of the victim net 12. FIG. 1B is a diagram depicting an example of delay noise 16 induced on the victim net. In the example illustrated in FIG. 1B, a rising transition 8 on the victim net 12 is slowed down or delayed as a result of a falling transition 14 on the aggressor net 10.
Thus, the crosstalk can have two major effects in modern digital circuits: (i) it can cause a strong glitch on a logically static signal, which may lead to functional fault if the glitch is sampled, and (ii) it can impact arrival time of a signal transition by speeding it up or slowing it down. The importance of the crosstalk effects has grown significantly with recent technology advances. For example, crosstalk delay has become a more prominent element of timing analysis during integrated circuit design due to factors such as, (i) increase in coupling-to-total capacitance ratio, (ii) decrease in supply voltage resulting in a reduction of gate overdrive (iii) shortening of clock period causing transition waveforms to play a bigger role, and (iv) tighter timing margins requiring more accurate timing analysis and less overestimation of delay.
Delay calculation in the presence of crosstalk typically involves finding a worst-case delay among possible aggressor alignments and aggressor waveforms. Determination of delay in the presence of aggressor-induced noise is a challenging task due to factors such as, (i) delay being sensitive to aggressor/victim alignment, (ii) linear models for switching drivers potentially being inaccurate due to drastic variation of impedance during transition, (iii) effective capacitance principle requiring modification (See, F. Dartu et al, supra), and (iv) waveforms potentially becoming nonmonotonic in the presence of noise, making the conventional metric of delay measurement non-robust.
In view of the sensitivity of crosstalk delay to factors such as, aggressor alignment, the nonlinearity of drivers, and aggressor timing window constraints, a search for the worst-case (WC) alignment may be approached using constrained nonlinear optimization techniques. However, optimization in a multidimensional space of aggressor alignments with each iteration requiring simulation of a nonlinear circuit can be prohibitively expensive. The crosstalk delay analysis task is further complicated by the potential for a unique waveform response of each receiver of a victim net to a given input transition, such that a WC aggressor alignment for one receiver may not be the same for another.
Another challenge with analyzing a crosstalk induced delay change arises from the potential for crosstalk to distort a victim switching waveform. A distorted waveform may deviate from the input waveforms used in delay characterization of a receiving gate, resulting in inaccuracy in slew dependent delays in a downstream logic cone. If the crosstalk impact is severe, the victim waveform may even become non-monotonic (bumpy), the effect of which may not be properly modeled in existing gate delay systems.
There have been prior proposals for analysis of crosstalk induced delay. R. Arunachalam, K. Rajagopal, and L. Pileggi. Taco, “Timing analysis with coupling”. Proceedings of the Design Automation Conference, pages 266-269, June 2000 teach that static timing analysis (STA) can be used to calculate delay while accounting for effects of switching aggressors using a heuristic-based Miller factor, which is applied to coupling capacitance before it is grounded. This approach is believed to be too conservative and inaccurate to be successfully used for modern design constraints.
Another approach is based on computation of a noisy transition—transition in the presence of switching aggressors, and using it for determining new slews and delays. In several studies the linear superposition principle was applied to the nominal transition with a noisy waveform on the victim net computed separately. See, F. Dartu, et al., supra.; R. Arunachalam, et al. supra; and P. D. Gross, R. Arunachalam, K. Rajagopal, and L. Pileggi, “Determination of worst-case aggressor alignment for delay calculation”, Proceedings of the ICCAD, pages 212-219, November 1998. The nominal transition is computed using a linear Thevenin model for the victim driver with all aggressors kept quiet. The alignment between nominal transition on the victim and transitions on the aggressors was chosen based on noise pulse width and height. However, since the noise wave was computed for a quiet victim driver and not a switching one, the alignment used in the mentioned studies could be inaccurate.
S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov, and J. Zuo, “Driver modeling and alignment for worst-case delay noise”, Proceedings of the Design Automation Conference, pages 720-725, June 2001, proposed that alignment between the victim and aggressors should be determined using characteristics of a receiving gate. The proposed approach is based on a pre-characterized 4-D look-up table representing alignment as a function of nominal slew rate, noise peak and width on the victim net and output load of receiving gate.
Current-based models for gates have been proposed. See, J. F. Croix, and D. F. Wong, “Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models”, In Proceedings of the Design Automation Conference, 386-391, June 2003; and V. Zolotov, D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon and R. Levy, “Noise propagation and failure criterion for VLSI designs” Proceedings of the ICCAD, pages 587-594, November 2002. However, there is no teaching of how such current model is to be integrated in a flow of crosstalk delay change analysis.
FIGS. 3A and 3B illustrate one aspect of a conventional methodology for measurement of aggressor-induced crosstalk delay. FIG. 3A is an illustrative drawing of a set of curves that represent victim signal transitions from VDD to ground. Each curve represents a different alignment of a victim signal transition with an aggressor signal. In each case, the aggressor signal induces a bump in the victim signal transition. The curves are non-monotonic due to the aggressor-induced bumps. Victim net signal transition delay is measured in terms of the time at which the victim signal crosses the Vref level. The curves of FIG. 3A illustrate that an aggressor-induced bump can cause the victim signal to cross Vref multiple times. A second crossing increases the measured victim signal transition delay according to the conventional methodology, since the delay should be measured based on the latest crossing of Vref.
FIG. 3B is an illustrative drawing of a curve representing victim signal transition delay versus aggressor alignment. The heavy dots on the delay curve denote corresponding crossing times of Vref on the noisy transitions shown in FIG. 3A. The curve of FIG. 3B shows that victim signal transition delay depends upon aggressor alignment. Unfortunately, the non-monotonic waveforms of FIG. 3A result in a ‘cliff’ in the curve of FIG. 3B methodology. The last curve in FIG. 3A does not have a bump crossing Vref, which engenders the cliff in delay curve in FIG. 3B. This prior methodology is not robust because even a relatively small change in a circuit parameter (e.g., driver size, supply voltage, etc) and/or aggressor alignment on a particular victim net can result in a disproportionate change in measured victim signal delay due to such cliff.
Because the crosstalk can cause two types of effect as outlined above, it is desired that there be two signal integrity analyses for signoff: (i) crosstalk glitch (functional noise) analysis, and (ii) noise-on-delay analysis. Both forms of signal integrity analysis can be computationally costly, and often affect the time-to-market characteristics of design methodology. The most expensive parts of a signal integrity analysis tend to be (i) RC reduction and (ii) solving the reduced network. The run time of the mentioned process grows super-linearly as the number of aggressor nets increases. There is a need, therefore, for an efficient and relatively accurate method of handling a larger number of small aggressors.
Modeling of small aggressors accurately and efficiently is an important factor in quality of noise and noise-on-delay analysis. A popular approach to modeling the high number of small aggressors is based on Virtual Aggressor (VA). The VA modeling consists of two major aspects: Modification of coupled RC network, where small aggressors are “lumped” into a single node representing a virtual aggressor, and construction of a driver model for the virtual aggressor, which is required for calculation of a response on the victim and contribution of virtual aggressor into noise.
Lumping multiple aggressors into a single virtual aggressor is schematically depicted in FIG. 2. As shown in this Figure, all the coupling capacitors connecting the small aggressors, a1-an, and the victim net, V, are reconnected to the Virtual Aggressor VA. While one of the capacitors' terminals are “lumped” together, the other terminals are still distributed on the victim net. In addition to reconnecting the capacitors, their value can be reduced by a factor taking into account a low probability that all the small aggressors will switch at the same time and in a certain direction.
One of the first implementations of the virtual aggressor concept was done several years ago in Cadence's SI analysis tool CeltIC. It allowed a significant improvement of CeltIC's run time mainly due to a much lower number of aggressor nets and parasitic elements in the net complex. At the same time, the initial implementation of VA in CeltIC suffered from several significant drawbacks resulting in additional inaccuracy of the analysis.
One technique for determining whether an aggressor can be included in a virtual aggressor is based on the magnitude of its impact on the victim. Particularly, the aggressor net is included in the virtual aggressor if the height of the glitch it causes on a victim is less than a predetermined factor of the supply voltage. For example, the aggressor net is included into the virtual aggressor if:H<Gtol*Vdd. 
Here Vdd is supply voltage on the victim net and Gtol is a user-defined parameter. Generally speaking, the larger the value selected for Gtol, the greater the number of aggressors included in the virtual aggressor. If the aggressor net is not below this threshold, it remains a distinct aggressor.
Because the timing restrictions on transitions on the aggressor nets can limit the impact an aggressor has on the victim, conventional virtual aggressor methodologies apply timing window limitations to the capacitive modification process. These timing window restrictions are conventionally used to restrict the total added capacitance. However, because timing window limitations are calculated in advance, they do not take into account the dynamic nature of such limitations. As such, they can become overly pessimistic and expensive.